module vga_ctrl (
    input   wire            clk25M      ,
    input   wire            rst_n       ,
    input   wire    [23:0]  data_in     ,

    output  reg     [9:0]   hcount      ,
    output  reg     [9:0]   vcount      ,
    output  reg     [23:0]  vga_rgb     ,

    output  wire            vga_hs      ,
    output  wire            vga_vs      ,
    output  wire            vga_blk     ,
    output  wire            vga_clk     

);

assign vga_clk = ~clk25M;

reg [9:0]   hcount_r, vcount_r;
wire hcount_ov, vcount_ov;
wire dat_act;

parameter   VGA_HS_end = 10'd95,
            hdat_begin = 10'd143,
            hdat_end = 10'd783,
            hpixel_end = 10'd799,
            VGA_VS_end = 10'd1,
            vdat_begin = 10'd34,
            vdat_end = 10'd514,
            vline_end = 10'd524;

assign hcount = dat_act?(hcount_r-hdat_begin):10'd0;
assign vcount = dat_act?(vcount_r-vdat_begin):10'd0;

always @(posedge clk25M or negedge rst_n) begin
    if(!rst_n)
        hcount_r <= 10'd0;
    else if(hcount_ov)
        hcount_r <= 10'd0;
    else 
        hcount_r <= hcount_r + 10'd1;
end

assign hcount_ov = (hcount_ov == hpixel_end);

always @(posedge clk25M or negedge rst_n) begin
    if(!rst_n)
        vcount_r <= 10'd0;
    else if (hcount_ov)begin
        if(vcount_ov)
            vcount_r <= 10'd0;
        else 
            vcount_r <= vcount_r + 10'd1;
    end
    else 
        vcount_r <= vcount_r;
end

assign vcount_ov = (vcount_r == vline_end);

assign dat_act = ((hcount_r >= hdat_begin) && (hcount_r < hdat_end))
                    &&((vcount_r>= vdat_begin) && (vcount_r < vdat_end));
assign vga_blk = dat_act;

assign vga_hs = (hcount_r > VGA_HS_end);
assign vga_vs = (vcount_r > VGA_VS_end);
assign vga_rgb = (dat_act)?data_in:24'h000000;

endmodule //vga_ctrl